Computer graphics products are now available which allow the researcher to study or view various types of data on a display screen. Such graphic systems typically incorporate a graphics processing unit (GPU) in conjunction with several types of memory as well as various latches, buffers and transceivers. The graphics system is generally utilized in relation to a host processor. The host processor generates the "raw data" which the graphics system places into a desirable video format for display purposes.
One such system has been developed in relation to the TMS34020 graphics processor manufactured and sold by Texas Instruments Corporation of Dallas, Tex. In that graphics display system, the GPU is connected via latching transceivers and buffers to separate video memory, dynamic program memory and static interface memory. The video memory includes a series of VRAMs arranged for parallel reception of display information generated by the GPU. The data stored in video memory is placed in serial form by way of a serial register and operated upon by a so-called palette device prior to final provision to a video device. The program memory is described as including a series of dynamic random access memory (DRAM) chips. The video memory is arranged in an x-y addressable format while the program memory is arranged for linear addressing. The program memory is intended for program execution information.
The problem with such graphics display systems is that not only are multiple memories provided for different address formatted information, but typically a good portion of the VRAM memory is wasted. As used herein, the term "display memory" refers to that portion of the memory which is utilized to store display type information and the term "offscreen memory" is used to refer to that portion of memory contained in the video memory which does not contain display information. Consider for the moment a 1280.times.1024 resolution display which utilizes eight bits per pixel. Such a display would most likely use two megabytes of VRAM in order to store display information in an x-y addressable block. Such a video memory will result in approximately 0.75 megabytes of useless offscreen memory. In the past, such memory has been used for x-y addressable purposes such as font storage, rectangular blits, etc. Consequently, the use of multiple memories with the resulting waste of offscreen memory is both inefficient and costly. Additionally, the use of dynamic ram in the program memory is not without its own difficulties, for example the use of multiplex addresses. See for example P. Horowitz, et al., The Art of Electronics (2nd Edition), New York, Press Syndicate of the University of Cambridge, 1989, p. 813-816.
It is noted that the TMS 34020 does support a so-called packed pixel array scheme by providing a midline reload capability which results in a contiguous unused memory beginning at the address after the last pixel. Using such a scheme, it may be possible to utilize the remaining memory for other purposes. Unfortunately, several problems result from such use. A strong penalty in graphics performance is incurred if the screen pitch is not a power of two. For example if the screen pitch were 1280, the packed pixel array scheme results in a 33% reduction in speed performance. Speed performance is worse if the screen pitch is not a sum of two numbers each of which are a power of two. Additionally, the packed pixel array scheme provides no mechanism for using unused portions of the video memory in a manner which is contiguous to any system memory.
Consequently, a need exists for a graphics system which maximizes memory usage, but yet is flexible enough to permit the use of additional memory devices.